In producing the silicon wafer, there are many processes which are performed while the back side of the silicon wafer is held in contact with a supporting member or a suction member and kept in a horizontal position. Examples of the processes include a silicon wafer conveying step, a heat treatment process in which a vertical boat is used, an RTA (rapid thermal annealing) process, a single-feed type epitaxial growth process, and an SOI heat treatment process. The processes are performed while the silicon wafer back side is held in contact with the supporting member or the suction member and kept in a horizontal position.
Recently, since a highly integrated device is produced in a generation of stepped-up miniaturization with increasing diameter of the wafer, it is necessary to decrease the number of scratches to be caused by the contact between the wafer and the supporting member as few as possible. Therefore, in handling the silicon wafer, there arise unavoidable circumstances to adopt an edge handling system in which only edges are held while the silicon wafer is not held at its back side by the suction member and the like.
For example, Japanese Patent Application Publication (Kokai) No. 2002-33378 discloses a handling apparatus including an end-effecting member which is freely movable in a vertical direction and at least three chuck-finger members which are attached to the end-effecting member and which have lower end portions used as a flange portion. An upper surface portion of the flange portion of the chuck-finger members is formed into a tapered surface, the end-effecting member is lowered and set sideways in the vicinity of wafer circumference from above the wafer, and the chuck-finger members are closed to hold the wafer on its tapered surface. It is said that the thin wafer which is hardly held by a conventional back side suction method or clamping method can stably be handled without generating deformation or fracture of the wafer since force is not applied to the wafer from the chuck-finger members.
On the other hand, conventionally a silicon wafer having crystal orientation <100> or <111> is mainly used to produce a semiconductor element. Recently, since carrier mobility of the semiconductor element largely depends on the crystal orientation of the wafer, attention focuses on the use of a silicon wafer having crystal orientation <110> in response to demands on a high-speed operation of the semiconductor element, and needs for the silicon wafer having the crystal orientation <110> are growing. This is because the use of the silicon wafer having the crystal orientation <110> can increase the carrier mobility to expect the achievement of the high-speed operation such as switching speed in the semiconductor element.
However, in a silicon wafer having crystal {110} plane as its principal surface, when compared with a silicon wafer having crystal {100} plane as its principal surface which is currently a mainstream wafer, contact scratches are easily generated in an outer circumferential portion, and unfortunately the wafer is easily fractured by development of the crack initiated from contact scratches. This is not limited to the silicon wafer having {110} plane as its principal surface, but a silicon wafer having {100} plane as its principal surface is also somewhat easily fractured in a specific direction, compared with other directions.
The edge handling alone disclosed in Japanese Patent Application Publication (Kokai) No. 2002-33378 is an ineffective countermeasure against such fracture caused by contact scratches.